? semiconductor components industries, llc, 2000 september, 2004 ? rev. xxx 1 publication order number: MTP75N03HDL/d MTP75N03HDL preferred device power mosfet 75 amps, 25 volts, logic level n?channel to?220 this power mosfet is designed to withstand high energy in the avalanche and commutation modes. the energy efficient design also offers a drain?to?source diode with a fast recovery time. designed for low?voltage, high?speed switching applications in power supplies, converters and pwm motor controls, and inductive loads. the avalanche energy capability is specified to eliminate the guesswork in designs where inductive loads are switched, and to offer additional safety margin against unexpected voltage transients. ? spice parameters available ? diode is characterized for use in bridge circuits ? i dss and v ds(on) specified at elevated temperature ? avalanche energy specified maximum ratings (t c = 25 c unless otherwise noted) rating symbol value unit drain?source voltage v dss 25 vdc drain?gate voltage (r gs = 1.0 m w ) v dgr 25 vdc gate?source voltage ? continuous ? single pulse (t p 10 ms) v gs 15 20 vdc vpk drain current ? continuous ? continuous @ 100 c ? single pulse (t p 10 m s) i d i d i dm 75 59 225 adc apk total power dissipation derate above 25 c p d 150 1.0 watts w/ c operating and storage temperature range t j , t stg ?55 to 175 c single pulse drain?to?source avalanche energy ? starting t j = 25 c (v dd = 25 vdc, v gs = 5.0 vdc, i l = 75 apk, l = 0.1 mh, r g = 25 w ) e as 280 mj thermal resistance ?junction to case ?junction to ambient r q jc r q ja 1.0 62.5 c/w maximum lead temperature for soldering purposes, 1/8 from case for 10 seconds t l 260 c 75 amperes 25 volts r ds(on) = 9 m w preferred devices are recommended choices for future use and best overall value. device package shipping ordering information MTP75N03HDL to?220ab 50 units/rail to?220ab case 221a style 5 1 2 3 4 http://onsemi.com n?channel d s g marking diagram & pin assignment MTP75N03HDL = device code ll = location code y = year ww = work week MTP75N03HDL llyww 1 gate 3 source 4 drain 2 drain
MTP75N03HDL http://onsemi.com 2 electrical characteristics (t j = 25 c unless otherwise noted) characteristic symbol min typ max unit off characteristics drain?source breakdown voltage (c pk 2.0) (note 3.) (v gs = 0 vdc, i d = 0.25 ma) temperature coefficient (positive) v (br)dss 25 ? ? vdc mv/ c zero gate voltage drain current (v ds = 25 vdc, v gs = 0 vdc) (v ds = 25 vdc, v gs = 0 vdc, t j = 125 c) i dss ? ? ? ? 100 500 m adc gate?body leakage current (v gs = 20 vdc, v ds = 0 v) i gss ? ? 100 nadc on characteristics (note 1.) gate threshold voltage (c pk 3.0) (note 3.) (v ds = v gs , i d = 0.25 ma) temperature coefficient (negative) v gs(th) 1.0 1.5 2.0 vdc mv/ c static drain?source on?resistance (c pk 2.0) (note 3.) (v gs = 5.0 vdc, i d = 37.5 adc) r ds(on) ? 6.0 9.0 m w drain?source on?voltage (v gs = 10 vdc) (i d = 75 adc) (i d = 37.5 adc, t j = 125 c) v ds(on) ? ? ? 0.68 0.6 vdc forward transconductance (v ds = 3.0 vdc, i d = 20 adc) g fs 15 55 ? mhos dynamic characteristics input capacitance (v 25 vd v 0vd c iss ? 4025 5635 pf output capacitance (v ds = 25 vdc, v gs = 0 vdc, f = 1.0 mhz ) c oss ? 1353 1894 reverse transfer capacitance f = 1 . 0 mhz) c rss ? 307 430 switching characteristics (note 2.) turn?on delay time t d(on) ? 24 48 ns rise time (v ds = 15 vdc, i d = 75 adc, v gs =50vdc t r ? 493 986 turn?off delay time v gs = 5.0 vdc, r g = 4.7 w ) t d(off) ? 60 120 fall time r g 4.7 w ) t f ? 149 300 gate charge q t ? 61 122 nc (v ds = 24 vdc, i d = 75 adc, q 1 ? 14 28 (v ds 24 vdc , i d 75 adc , v gs = 5.0 vdc) q 2 ? 33 66 q 3 ? 27 54 source?drain diode characteristics forward on?voltage (i s = 75 adc, v gs = 0 vdc) (i s = 75 adc, v gs = 0 vdc, t j = 125 c) v sd ? ? 0.97 0.87 1.1 ? vdc reverse recovery time t rr ? 58 ? ns (i s = 75 adc, v gs = 0 vdc, t a ? 27 ? (i s 75 adc , v gs 0 vdc , di s /dt = 100 a/ m s) t b ? 30 ? reverse recovery stored charge q rr ? 0.088 ? m c 1. pulse test: pulse width 300 m s, duty cycle 2%. 2. switching characteristics are independent of operating junction temperature. 3. reflects typical values. c pk = max limit ? typ 3 x sigma
MTP75N03HDL http://onsemi.com 3 typical electrical characteristics r ds(on) , drain-to-source resistance (ohms) r ds(on) , drain-to-source resistance (normalized) v ds , drain-to-source voltage (volts) figure 1. on?region characteristics i d , drain current (amps) i d , drain current (amps) v gs , gate-to-source voltage (volts) figure 2. transfer characteristics r ds(on) , drain-to-source resistance (ohms) i d , drain current (amps) figure 3. on?resistance versus drain current and temperature i d , drain current (amps) figure 4. on?resistance versus drain current and gate voltage t j , junction temperature ( c) figure 5. on?resistance variation with temperature v ds , drain-to-source voltage (volts) figure 6. drain?to?source leakage current versus voltage i dss , leakage (na) t j = 25 c v ds 10 v t j = 100 c 25 c -55 c t j = 25 c v gs = 0 v v gs = 10 v v gs = 5 v v gs = 5 v v gs = 10 v i d = 37.5 a 0.4 0.8 1.2 1.6 2 0 0.2 0.6 1 1.4 1.8 30 60 90 120 150 0 2 2.5 3.5 4 4.5 1.5 30 60 90 120 150 0 3 30 60 90 120 150 0 0.01 0.002 0.008 0.006 0.004 25 50 100 125 150 0 0.005 0.006 0.007 0.008 0.009 0.004 75 25 100 150 -50 -25 0 50 75 125 0.4 0.8 1.2 1.6 2 0 10 20 30 0 5 15 25 10 100 1000 10000 1 10 v 100 c 25 c t j = 125 c 100 c 25 c t j = -55 c 3.5 v 3 v 4 v 2.5 v 4.5 v 5 v 8 v 6 v
MTP75N03HDL http://onsemi.com 4 power mosfet switching switching behavior is most easily modeled and predicted by recognizing that the power mosfet is charge controlled. the lengths of various switching intervals ( d t) are determined by how fast the fet input capacitance can be charged by current from the generator. the published capacitance data is difficult to use for calculating rise and fall because drain?gate capacitance varies greatly with applied voltage. accordingly, gate charge data is used. in most cases, a satisfactory estimate of average input current (i g(av) ) can be made from a rudimentary analysis of the drive circuit so that t = q/i g(av) during the rise and fall time interval when switching a resistive load, v gs remains virtually constant at a level known as the plateau voltage, v sgp . therefore, rise and fall times may be approximated by the following: t r = q 2 x r g /(v gg ? v gsp ) t f = q 2 x r g /v gsp where v gg = the gate drive voltage, which varies from zero to v gg r g = the gate drive resistance and q 2 and v gsp are read from the gate charge curve. during the turn?on and turn?off delay times, gate current is not constant. the simplest calculation uses appropriate values from the capacitance curves in a standard equation for voltage change in an rc network. the equations are: t d(on) = r g c iss in [v gg /(v gg ? v gsp )] t d(off) = r g c iss in (v gg /v gsp ) the capacitance (c iss ) is read from the capacitance curve at a voltage corresponding to the off?state condition when calculating t d(on) and is read at a voltage corresponding to the on?state when calculating t d(off) . at high switching speeds, parasitic circuit elements complicate the analysis. the inductance of the mosfet source lead, inside the package and in the circuit wiring which is common to both the drain and gate current paths, produces a voltage at the source which reduces the gate drive current. the voltage is determined by ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex. the mosfet output capacitance also complicates the mathematics. and finally, mosfets have finite internal gate resistance which effectively adds to the resistance of the driving source, but the internal resistance is difficult to measure and, consequently, is not specified. the resistive switching time variation versus gate resistance (figure 9) shows how typical switching performance is affected by the parasitic circuit elements. if the parasitics were not present, the slope of the curves would maintain a value of unity regardless of the switching speed. the circuit used to obtain the data is constructed to minimize common inductance in the drain and gate circuit loops and is believed readily achievable with board mounted components. most power electronic loads are inductive; the data in the figure is taken with a resistive load, which approximates an optimally snubbed inductive load. power mosfets may be safely operated into an inductive load; however, snubbing reduces switching losses. gate-to-source or drain-to-source voltage (volts) c, capacitance (pf) figure 7. capacitance variation v gs v ds t j = 25 c v ds = 0 v v gs = 0 v 15000 12000 9000 6000 3000 0 20 25 10 15 05 10 5 c rss c iss c oss c rss c iss
MTP75N03HDL http://onsemi.com 5 v ds , drain-to-source voltage (volts) v gs , gate-to-source voltage (volts) figure 8. gate?to?source and drain?to?source voltage versus total charge figure 9. resistive switching time variation versus gate resistance r g , gate resistance (ohms) 1 10 100 t, time (ns) t j = 25 c i d = 75 a v dd = 15 v v gs = 5 v t r t f t d(off) t d(on) 0 q t , total gate charge (nc) 10 20 30 40 70 t j = 25 c i d = 75 a 10000 1000 100 10 6 4 2 0 7 5 3 1 28 24 20 16 12 8 4 50 60 0 qt q1 q3 v gs v ds q2 drain?to?source diode characteristics the switching characteristics of a mosfet body diode are very important in systems using it as a freewheeling or commutating diode. of particular interest are the reverse recovery characteristics which play a major role in determining switching losses, radiated noise, emi and rfi. system switching losses are largely due to the nature of the body diode itself. the body diode is a minority carrier device, therefore it has a finite reverse recovery time, t rr , due to the storage of minority carrier charge, q rr , as shown in the typical reverse recovery wave form of figure 12. it is this stored charge that, when cleared from the diode, passes through a potential and defines an energy loss. obviously, repeatedly forcing the diode through reverse recovery further increases switching losses. therefore, one would like a diode with short t rr and low q rr specifications to minimize these losses. the abruptness of diode reverse recovery effects the amount of radiated noise, voltage spikes, and current ringing. the mechanisms at work are finite irremovable circuit parasitic inductances and capacitances acted upon by high di/dts. the diode's negative di/dt during t a is directly controlled by the device clearing the stored charge. however, the positive di/dt during t b is an uncontrollable diode characteristic and is usually the culprit that induces current ringing. therefore, when comparing diodes, the ratio of t b /t a serves as a good indicator of recovery abruptness and thus gives a comparative estimate of probable noise generated. a ratio of 1 is considered ideal and values less than 0.5 are considered snappy. compared to on semiconductor standard cell density low voltage mosfets, high cell density mosfet diodes are faster (shorter t rr ), have less stored charge and a softer reverse recovery characteristic. the softness advantage of the high cell density diode means they can be forced through reverse recovery at a higher di/dt than a standard cell mosfet diode without increasing the current ringing or the noise generated. in addition, power dissipation incurred from switching the diode will be less due to the shorter recovery time and lower switching losses. v sd , source-to-drain voltage (volts) i s , source current (amps) t j = 25 c v gs = 0 v figure 10. diode forward voltage versus current 0.6 0.7 0.8 0.9 1 0.5 0 15 30 45 60 75
MTP75N03HDL http://onsemi.com 6 safe operating area the forward biased safe operating area curves define the maximum simultaneous drain?to?source voltage and drain current that a transistor can handle safely when it is forward biased. curves are based upon maximum peak junction temperature and a case temperature (t c ) of 25 c. peak repetitive pulsed power limits are determined by using the thermal response data in conjunction with the procedures discussed in an569, atransient thermal resistance?general data and its use.o switching between the off?state and the on?state may traverse any load line provided neither rated peak current (i dm ) nor rated voltage (vdss) is exceeded, and that the transition time (t r , t f ) does not exceed 10 m s. in addition the total power averaged over a complete switching cycle must not exceed (t j(max) ? t c )/(r q jc ). a power mosfet designated e?fet can be safely used in switching circuits with unclamped inductive loads. for reliable operation, the stored energy from circuit inductance dissipated in the transistor while in avalanche must be less than the rated limit and must be adjusted for operating conditions differing from those specified. although industry practice is to rate in terms of energy, avalanche energy capability is not a constant. the energy rating decreases non?linearly with an increase of peak current in avalanche and peak junction temperature. although many e?fets can withstand the stress of drain?to?source avalanche at currents up to rated pulsed current (i dm ), the energy rating is specified at rated continuous current (i d ), in accordance with industry custom. the energy rating must be derated for temperature as shown in the accompanying graph (figure 13). maximum energy at currents below rated continuous i d can safely be assumed to equal the values indicated. 0.1 100 r ds(on) limit thermal limit package limit 10 v gs = 20 v single pulse t c = 25 c 1 10 100 1000 1 dc 100 m s 1 ms 10 ms t j , starting junction temperature ( c) e as , single pulse drain-to-source figure 11. maximum rated forward biased safe operating area v ds , drain-to-source voltage (volts) figure 12. maximum avalanche energy versus starting junction temperature avalanche energy (mj) i d , drain current (amps) 25 50 75 100 125 i d = 75 a 150 80 280 200 160 120 240 40 0
MTP75N03HDL http://onsemi.com 7 typical electrical characteristics r q jc (t) = r(t) r q jc d curves apply for power pulse train shown read time at t 1 t j(pk) - t c = p (pk) r q jc (t) p (pk) t 1 t 2 duty cycle, d = t 1 /t 2 t, time (s) figure 13. thermal response r(t), normalized effective transient thermal resistance figure 14. diode reverse recovery waveform di/dt t rr t a t p i s 0.25 i s time i s t b 1.0 0.1 0.01 0.2 d = 0.5 0.05 0.01 single pulse 0.1 1.0e-05 1.0e-04 1.0e-03 1.0e-02 1.0e-01 1.0e+00 1.0e+01 0.02
MTP75N03HDL http://onsemi.com 8 package dimensions to?220 three?lead to?220ab case 221a?09 issue aa style 5: pin 1. gate 2. drain 3. source 4. drain notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: inch. 3. dimension z defines a zone where all body and lead irregularities are allowed. dim min max min max millimeters inches a 0.570 0.620 14.48 15.75 b 0.380 0.405 9.66 10.28 c 0.160 0.190 4.07 4.82 d 0.025 0.035 0.64 0.88 f 0.142 0.147 3.61 3.73 g 0.095 0.105 2.42 2.66 h 0.110 0.155 2.80 3.93 j 0.018 0.025 0.46 0.64 k 0.500 0.562 12.70 14.27 l 0.045 0.060 1.15 1.52 n 0.190 0.210 4.83 5.33 q 0.100 0.120 2.54 3.04 r 0.080 0.110 2.04 2.79 s 0.045 0.055 1.15 1.39 t 0.235 0.255 5.97 6.47 u 0.000 0.050 0.00 1.27 v 0.045 --- 1.15 --- z --- 0.080 --- 2.04 b q h z l v g n a k f 123 4 d seating plane ?t? c s t u r j on semiconductor and are trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to make changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. atypicalo parameters which may be provided in scill c data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including atypicalso must be validated for each customer application by customer's technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body , or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthori zed use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. publication ordering information central/south america: spanish phone : 303?308?7143 (mon?fri 8:00am to 5:00pm mst) email : onlit?spanish@hibbertco.com toll?free from mexico: dial 01?800?288?2872 for access ? then dial 866?297?9322 asia/pacific : ldc for on semiconductor ? asia support phone : 303?675?2121 (tue?fri 9:00am to 1:00pm, hong kong time) toll free from hong kong & singapore: 001?800?4422?3781 email : onlit?asia@hibbertco.com japan : on semiconductor, japan customer focus center 4?32?1 nishi?gotanda, shinagawa?ku, tokyo, japan 141?0031 phone : 81?3?5740?2700 email : r14525@onsemi.com on semiconductor website : http://onsemi.com for additional information, please contact your local sales representative. MTP75N03HDL/d north america literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303?675?2175 or 800?344?3860 toll free usa/canada fax : 303?675?2176 or 800?344?3867 toll free usa/canada email : onlit@hibbertco.com fax response line: 303?675?2167 or 800?344?3810 toll free usa/canada n. american technical support : 800?282?9855 toll free usa/canada europe: ldc for on semiconductor ? european support german phone : (+1) 303?308?7140 (mon?fri 2:30pm to 7:00pm cet) email : onlit?german@hibbertco.com french phone : (+1) 303?308?7141 (mon?fri 2:00pm to 7:00pm cet) email : onlit?french@hibbertco.com english phone : (+1) 303?308?7142 (mon?fri 12:00pm to 5:00pm gmt) email : onlit@hibbertco.com european toll?free access*: 00?800?4422?3781 *available from germany, france, italy, uk, ireland
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